Memory devices typically include an array of memory cells that are accessed on a grid of rows and columns. For semiconductor memory architectures such as Static Random Access Memory (SRAM) and Dynamic Random Access Memory (DRAM), rows and columns are referred to as wordlines and bitlines, respectively. To decrease capacitance on the bitlines and thereby improve performance of the memory device, a memory cell array may be divided into memory banks that limit the number of rows in each bank. However, previous solutions require a local input/output (I/O) circuit specific to each bank which increases the area overhead of the memory device. Subsequent solutions dispose local I/O circuitry between memory banks so that up to two memory banks, but not more, may share the same I/O circuitry.